Original press release published here.

SAN JOSE, Calif. –March 31, 2025 – Ayar Labs, the leader in optical interconnect solutions for large-scale AI workloads, today announced the industry’s first Universal Chiplet Interconnect Express™ (UCIe™) optical interconnect chiplet to maximize AI infrastructure performance and efficiency while reducing latency and power consumption. By incorporating a UCIe electrical interface, this solution is designed to eliminate data bottlenecks and integrate easily into customer chip designs.

Capable of achieving 8 Tbps bandwidth, the TeraPHY™ optical I/O chiplet is powered by Ayar Labs’ 16-wavelength SuperNova™ light source. The integration of a UCIe interface means this solution not only delivers high performance and efficiency but also enables interoperability among chiplets from different vendors. This compatibility with the UCIe standard creates a more accessible, cost-effective ecosystem, which streamlines the adoption of advanced optical technologies necessary for scaling AI workloads and overcoming the limitations of traditional copper interconnects.

“Optical interconnects are needed to solve power density challenges in scale-up AI fabrics,” said Mark Wade, CEO and co-founder of Ayar Labs. “We recognized early on the potential for co-packaged optics, which positioned us to drive adoption of optical solutions in AI applications. As we continue to push the boundaries of optical technologies, we’re also bringing together the supply chain, manufacturing, and testing and validation processes needed for customers to deploy these solutions at scale.”

Ayar Labs has combined silicon photonics with CMOS manufacturing processes to enable the use of optical interconnects in a chiplet form factor within multi-chip packages. This allows GPUs and other accelerators to communicate across a wide range of distances, from millimeters to kilometers, while effectively functioning as a single, giant GPU.

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